1. Field of the Invention
The invention relates to solid state integrated circuit devices and more particulary to improved, miniaturized semiconductor integrated circuit devices.
2. Description of Related Art
Shockley, Bardeen, and Brattain invented the transistor around 1950 and started the modern electronics age. Kilby and Noyce next combined active and passive components on a single chip and invented the integrated circuit. Fairchild""s Isoplanar technology (FIG. 1) made possible medium-scale and larger-scale integrated circuits in 1972 according to Peltzer""s U.S. Pat. No. 3,648,125. Simultaneously, other similar dielectric isolation processes such as Kooi""s LOCOS (i.e., local oxide isolation technology) of Philip and Magdos""s oxide-recessed technology of IBM were also widely used. In a 1976 Interference No. 98,426, Li""s application No. 154,300 on round-bottomed isolating oxide groove was considered as the xe2x80x9cSeniormost Inventorxe2x80x9d among Fairchild""s Peltzer, Philip""s Kooi, and IBM""s Magdo and Magdo.
According to Peltzer""s patent, the Fairchild""s Isoplanar device 40 as typified by FIG. 4 in his patent has a n-type epitaxial silicon layer 42 formed on a p-type substrate 41. Oxide isolating regions, e.g., 44a, 44b, 44c, and 44d were used to isolate the different components. Each of these oxide isolating regions has a central flat bottom occupying much chip real estate producing unnecessarily larger devices.
Li""s round-bottomed isolating oxide groove 21 of FIG. 21 in 154,300 application improves device leakage current and breakdown voltage. The groove bottom G of zero width eliminates the wasted chip real estate of all other previously existing devices of, e.g., Isoplanar, LOCOS, and oxide-recessed types. This feature produces smaller devices. The oxide isolating regions in this present invention are further narrowed down to even one or two atomic layers occupying the minimum chip real estate. Li""s devices also have rounded PN junction peripheral surfaces minimizing contamination by micron-size or even atomic particles thereby increasing yields. See FIG. 2. The smaller the device size, the more critical this yield factor.
In the 154,300 patent application, the device of FIG. 2 is made by thermally growing an oxide groove, band, or material region 21 transversely into a p-type silicon substrate 22. This is followed by oxide-guided, maskless diffusion of n-type dopants from the top surface 23 to give the top n-type silicon layer 24 and the new PN junction region 25. The rounded bottom G has a zero bottom width.
All these devices can still be improved in performance and device size. The present invention provides still better and further miniaturized solid-state integrated circuits in general and semiconductor integrated circuits in particular.
Specifically, this invention will address the following issues:
1) improving the critical gate layer thickness and structure;
2) reducing the insulating field oxide region size by orders of magnitude from microns to Angstroms;
3) making the entire device more resistant to temperature, stress, impact, vibration, and high-gravity (G) forces due to rapid acceleration and deceleration;
4) simplifying a device material inventories and manufacturing process;
5) providing a new type of high-performance flexible circuits; and
6) designing three-dimensional (3-D) atomic or molecular diode or transistor arrays or circuits especially useful for supercomputers and electro-optical telecommunications.
The devices of the invention may use different solid-state or semiconductor materials including Si, Ge, Sixe2x80x94Ge, InP, GaAs, SiC, InAs, superconductor, and diamond. In this invention, Si semiconductor materials are exclusively used by way of illustration. Metal-oxide-semiconductor (MOS) or, in general, conductor-insulator-semiconductor (CIS) devices are used exclusively as examples in this specification. Other types of solid-state and semiconductor circuit devices are also useful. Specifically, electro optical, superconductor, magnetic, ferro electric memory, electrooptomagnetic, and other solid-state devices can also be designed according to principles of this invention.
The xe2x80x9cheartxe2x80x9d of the transistor is the gate dielectric, where most electronic actions and the associated device heating or degradations occur. The gate oxide is the smallest but a critical feature of the transistor. It lies between the transistor""s gate electrode, which turns current flow, and the silicon channel through which the current flows. The gate oxide insulates and protects the channel from the gate electrode preventing short circuits. Shrinking this oxide layer allows more current out of the switch with less voltage. More than any other part of the structure, this layer determines the device performance and reliability. Many think that this insulating layer would be the limiting factor for producing increasingly smaller chips.
The thickness of gate oxides is the subject of intense research. Bell Laboratory scientists have created a 5-atom silicon dioxide layer that included a 1-atom transition layer between this layer and substrate. A rapid thermal oxidation technique was used using pure oxygen at 1,000 C. for 10 seconds. Oxides less than 6 angstroms or 3 atoms have been made, but the leakage current was not manageable. Additional reliability issues included adhesion loss, texture, thermally or mechanically induced cracking, moisture adsorption, step coverage, and time-dependent behavior such as thermal conductivity, and breakdown voltage. The reduced mechanical strength is critical in both packaging and processing such as during chemical-mechanical polishing.
Traditionally, the gate dielectric is a thermally grown layer of silicon dioxide (SiO2) layer averaged about 25 atoms thick. By continually reducing the gate oxide thickness and the length of the gate electrode, the semiconductor industry has doubled the transistor""s switching speed every 18 to 24 months according to the Moores Law. This has worked remarkably well, but problems exist. One is that the oxide often permits boron penetration from the gate into the threshold region, degrading the threshold voltage and device performance. The other problem is that, as device size shrinks, the gate oxide becomes so thin that tunneling currents arise from the gate through the oxide to the substrate, again degrading the device performance.
To overcome the first problem, transistor engineers have developed solutions involving stacked gates and various nitridation techniques. Nitradation adds nitrogen to the silicon dioxide. A successful two-step oxidation/nitridation approach using a sequential in situ steam generation and rapid plasma nitridation process shows a 5-7 times reduction in current leakage compared to SiO2 at an effective oxide thickness of less than 20 A (or Angstroms).
The second problem relates to current tunneling through very thin oxide. This problem is more difficult and thought to require a change of materials. The tunneling current rises very quickly as the oxide is thinned down. It is believed that below about 14-15 A, new material must be used to replace the silicon dioxide. One would look for a thinner but defect-free SiO2 film to avoid the excessive leakage current. The new high-k materials must be put in place as the 14-15A SiO2 layers. Some solutions are possible, but none fit all needs.
The new insulating material must also have the right dielectric constant and be chemically compatible with silicon to get the right interface. Interface remains a critical and largely unknown area of research. Interface microengineering may in fact be the key factor that will allow the new or old materials to continue the scaling of field-effect transistors (FET).
The defect-free gate dielectric layer must be put down uniformly in a thin film to tolerate subsequent silicon processing and temperature cycling. There is still no suitable high dielectric constant material and interface layer with the stability and interface characteristics to serve as a gate dielectric.
Metal silicates may be good candidates. Hafnium and zirconium silicates are stable in contact with silicon, between substrate and dielectric. Tantalum pentoxide is also available.
Even with a material other than SiO2, a very thin SiO2 layer will probably still be required at the channel and/or gate electrode interface to preserve interface state characteristics and channel mobility. This would severely reduce any benefits due to the high-k dielectric. It is clear the first 10 A above the silicon substrate largely determine the leakage properties of the dielectric and the carrier mobilities in the channel underneath. Once past that, only the bulk properties of the film needs to be dealt with. Controlling these properties will be critical to the success of high-k materials. Some hope exists to shrink the silicon dioxide down to 0.1 um (or microns) thick using plasma nitridation to control the first 10 A or so of the dielectric.
The gate material is often a doped polysilicon with a silicide on top. Interest exists in switching the polysilicon to a metal due to depletion effects associated with the poly. When the device is turned on, the polysilicon actually depletes a little bit making it look like a thicker oxide. This depletion effect leads to less drive currentxe2x80x94a characteristic of a semiconductor material rather than a metal. Still, high dielectric (k) material is moving from the doped polysilicon now used to a metal.
The advantage of metal gates is that this depletion effect is avoided, and the gate resistance is lowered. But two disadvantages to metal gates arise. The metal work function of the gate is fixed by the metal. By comparison, the work function in polysilicon is controllable by varying doping of either n-type or p-type. This allows optimization of the threshold voltages for both the n-channel and p-channel transistor. Such an optimization is not possible with metal.
The main focus of present transistor engineering effort is to maximize the drive current. The present transistor is a current source charging a large capacitor. The higher the current source and the smaller the capacitance, the faster it charges. All the industry""s scaling efforts are toward improving the drive current at lower voltages. Second to optimizing the drive current is a need to reduce parasitic capacitances at the device and interconnect levels.
Sixteen (16) ion implantation steps are commonly used to create the sources and drains for the PMOS and NMOS devices and the retrograde wells in which they sit. Implantation is also used to dope the gates and to provide the xe2x80x9cpunchthrough stopxe2x80x9d pockets. After the implantation, the device must be annealed at a relatively high temperature to remove the implantation damages, to xe2x80x9cactivatexe2x80x9d the dopants, and to insure that all dopant atoms lie exactly where needed.
The junction depth for source/drains should be only 35-70 nm deep for the 100 nm (or 0.1 um) generation due to go into production in 2005. Drain extensions should only be less than 20-33 nm deep. The abruptness of the source and drain extensions is critical. There are still no known solutions in several areas. Many believe computer modeling will help researchers determine the optimal doping profile and study the impact of various process parameters on dopant diffusion. A few degrees in temperature can have a significant effect on the doping profiles. Aggressive scaling of the transistor source/drain junction depth requires production-worthy (milli-Amps for 300 nm wafers) ion beam current at sub-Kev energies for boron. The requirement for sub-Kev implants is primarily driven by the need to reduce transient enhanced diffusion. Sputtering related dopant loss and other phenomena will likely preclude using sub-Kev implant energies below 0.5 Kev regardless of available beam current.
Reducing the implant energy, and annealing time and dose is of primary importance for achieving the shallowest junctions. Ultra-fast ramp-up rates are of secondary importance. Their potential benefit can only be captured with an equally fast but not achievable ramp-down rate. Several combinations of implant and annealing parameters (implant energy or dose, and annealing temperature, time and ramp rates) are possible that yield the same junction solutions. It is essential to select solutions which optimize manufacturability.
The semiconductor industry continues to require doubling device functionality every two years or so. It is thought this requires switching to new materials. Instead of aluminum, silicon dioxide, and polysilicon, some think that future integrated circuits will be built from copper, low-dielectrics and high-k dielectrics, and xe2x80x9cexoticxe2x80x9d metals like hafnium and zirconium.
The traditional silicon dioxide gate insulator needs close thickness control and low defect density. These may be met by improved cleaning and oxidation techniques. As the required layer becomes thinner, leakage currents and reliability problems arise. Direct tunneling can occur in very thin layers, giving high leakage current. At 100 degrees C., the maximum voltage rating of a 2.5 nm thick layer of silicon dioxide is only 1.5 V.
A silicon dioxide/dual-doped polysilicon gate stack process is used as the mainstay of CMOS device manufacturing since its inception. The new critical CMOS gate stack process would require high-k dielectric gate insulators, with a dual metal gate electrode. The use of this new process should be no later than five years. This is generally thought impossible.
A flowable oxide based on hydrogen silsesquioxane is often used to form ultrathin low-k insulating layers. Use of these layers reduces parasitic capacitance shortening propagation delays. These changes increase by 30% the within-chip processing speed as compared with other 180 nm CMOS processes. processes.
High-k dielectrics are one of the major road blocks in device scaling. With extremely smooth gate dielectric and very small channel length, the transistor drive current goes ballistic, increasing the input current flows via the channel from the usual 35% to 85%. The remaining input current collides with the rough edges of the insulating layer.
Low-k polymer dielectrics have been used to replace glass insulators and to separate the new copper wires in its new chips. Copper lead wires are also replacing aluminum wires. This material combination will push chip speeds one-third faster than today""s fastest chips. There are, however, problems to using this system: 1) the plastic is much softer than glass and does not stay in place, making it difficult to make the chips; and 2) these polymers do not stick to other materials including silicon and other polymers.
Tungsten is replacing the aluminum interconnects. The use of tungsten reduces the conductor widths down to 240 nm below the normal metal layers at the gate level. The extra routing flexibility achieved by the local interconnect reduces 10-20% of the silicon area. The spacing between tracks in the first metal layer can be considerably increased to reduce sensitivity of this layer to defects thereby increasing device yields. However, the very high tungsten density of 19.3 (vs. 2.7 for Al and 2.33 for silicon or silicon dioxide) induces deboning of tungsten from other materials during fast accelerations and decelerations, as shown later.
The capacitance between the gate and channel of an insulated gate FET should be high. In small area devices, this cannot be achieved by using a very thin silicon dioxide layer, or the leakage current will be too high due to material imperfections. A polysilicon gate electrode has been used with germanium doping to control the work function of the material. A variety of metals will be tried as gate electrodes, with TiN/Al or TiN/W being the most likely candidates. Also considered is deposition of high-k gate insulators by the atomic layer chemical vapor deposition technique using aluminum oxide, hafnium oxide, titanium oxide, zirconium oxide and silicates of zirconium and hafnium.
Ballistic effects occur around the 30 nm channel length when the electrons emitted from the source arrive at the drain without scattering. Small dimensions have great impact on electrons. The channel lengths of conventional transistors are so long that electrons seldom go all the way from the source to the drain without scattering. But when the channel length gets down to around 35 nm, the ballistic component increases and device performance improves. However, once ballisting occurs, further reduction of the channel length no longer improves the performance. Electrons travel better when the gate oxide is slightly thicker because they are less attracted to the gate directly above the gate oxide layer.
There still is plenty of life left in traditional gate structure. Take, for example, the xe2x80x9cballistic nanotransistorsxe2x80x9d. In these devices, dramatic gains in drive current are possible simply by combining a very smooth gate dielectric with a short channel length, such as in Vertical MOSFET. The main challenge is to replace the traditional silicon dioxide/dual-doped polysilicon gate stack process. This stack process has been the mainstay of complementary metal-oxide-semiconductor (CMOS) device manufacturing since its inception. The new CMOS gate stack process will require cost-effective, low-temperature integration of nanometer scale high-k dielectric gate insulators, with dual metal gate electrodes. The replacement should be within five years. History has shown, however, that changes of this magnitude normally require at least ten years to implement.
The very slow progress in finding new semiconductor materials is looming as a grand challenge in chip design. There are still many, many problems that are material-limited. New material selection, design, and processing methods must be found. The whole manufacturing process is too complicated to achieve high repeatability and good device yield and performance. Most of the materials are not applied in optimal ways. This invention will address many of these issues.
A solid state device comprises a first semiconductor region of a first conductivity type; an insulating material region containing at a selected location therein at least one n-type or p-type dopant region and positioned on top of the semiconductor region; and a second semiconductor region of a second conductivity type and positioned on top of the insulating material region. The at least one dopant region in the insulating material region forms a PN junction region with either one of said first and second semiconductor regions. The PN junction is of no more than a size selected from the group consisting of one half of a micron, 0.1 micron, and 3 angstroms. A method of making the device is also disclosed.
To overcome the foregoing and other difficulties, the general object of this invention is to provide an improved, semiconductor or solid-state integrated circuit device with improved performance, yield, cost, and miniaturization;
A broad object of the invention is to provide an integrated semiconductor circuit with a submicron or Angstrom-thin isolating material layer to form at least one of the critical parts thereof.
Another object of the invention is to provide a new, improved gate or field layer which can be easily and rapidly produced at high yield and low cost.
Yet another object of the invention is to provide a new, improved field isolation layer that not only improves circuit performance but allows significant miniaturization.
A further object of the invention is to provide an integrated semiconductor circuit with an isolating material layer which is sufficiently thin and flexible, thereby not only advancing device miniaturization, but improving circuit performance and minimizing thermal or volume expansion mismatch stresses on the circuit.
Another object of the invention is to provide a new generation of low-cost environment-resistant flexible circuits.
A still further object of the invention to mass-produce, at low cost but high yields, wafer chips each containing thousands or millions of transistors more miniaturized than is presently possible.
Yet another object of the invention is to provide highly miniaturized electro-optical three-dimensional, integrated atomic or molecular diode or transistor arrays especially suitable for and optical telecommunication.